The process of designing a large and complex digital system includes reducing a system architecture to a high level behavioral system model and then translating the system model into an equivalent low level circuit model comprising logic devices and storage devices, such as gates and latches. The translation process may introduce errors into the circuit model, so another process known as logic verification is performed to identify errors introduced during the translation process. During the logic verification process, the functionality of the circuit model is compared to the functionality of the high level behavioral system model to ensure that the two models are functionally equivalent.
The logic verification process is implemented on systems characterized as primarily hardware based systems or on systems characterized as primarily software based systems. A hardware based system that performs logic verification of complex digital system models is known as a hardware emulator. A hardware emulator provides reasonable turnaround time for a small number of system designers and testers seeking to verify the performance of a digital system. Unfortunately, a hardware emulator has several disadvantages. First, being a custom solution tailored to the verification of a particular digital system design, a hardware emulator is a very expensive system to develop and replicate. Second, since a hardware emulator is expensive to replicate and since a single emulator can only support a small number of system designers and testers, it is difficult to reduce the design cycle time for a digital system without a large increase in capital expenditures.
Software based logic verification systems have been in use for many years. They are used extensively in the development of digital systems requiring only low or medium levels of circuit integration. Unfortunately, for complex digital systems, such as microprocessors, which are highly integrated devices, the development of traditional software based logic verification systems has not kept pace with the demands of verifying the performance of the large and complex digital systems.
For these and other reasons there is a need for the present invention.